(a) Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. In more detail, the present invention relates to a method of manufacturing a semiconductor device (including a combination of high voltage (HV) depletion-enhancement CMOS (DECMOS) devices and logic devices) that is capable of simultaneously forming medium voltage (MV) and high voltage devices.
(b) Description of the Related Art
In a process for manufacturing a liquid crystal display driver integrated circuit (LCD Driver IC, or LDI) according to a conventional art, a controller IC, a source driver IC, and a gate driver IC are usually formed as a three-chip solution or a two-chip solution.
Recently, a one-chip solution for mobile communication systems has been developed, so an advanced manufacturing method for a merged or combined process that can simultaneously form a semiconductor device for high voltage (HV) operation, for medium voltage (MV) operation, and for low voltage (LV) operation is needed and/or desired.
In a current level of semiconductor processes, a conventional process for a logic device and that for a high voltage operation device are separately performed in the merged or combined process, so the number of masks for the integrated solution (i.e., containing HV, MV and LV devices) is the same or larger. That is, although a junction that is used for the HV device is the same type as the logic device (the MV or LV device), separate photolithography processes for forming those junctions are performed.
In addition, a mask for forming a channel stop layer (typically used for isolating the HV operation device region) and masks for the typical process for a logic device are separately used. This is because the thermal budget for the high voltage operation device cannot be applied to the process for making a low voltage or a medium voltage operation device.
FIG. 1 is a cross-sectional view showing a semiconductor device formed with an NMOS drift region Ndrift (e.g., 116) and a PMOS drift region Pdrift (e.g., 117) in an HV device, made according to a conventional photolithography process using of separate masks. Referring to FIG. 1, in the conventional process for making the semiconductor device, additional masks are used for forming an Ndrift region (e.g., 116) and a Pdrift region (e.g., 117) in an HV region.
In more detail, a P-well 113 and an N-well 114 for an HV operation device, and an N-Well 115 for a logic device, are formed in a P-type semiconductor substrate 111, and then an Ndrift region 116 and a Pdrift region 117 for the HV operation device are formed using a different mask from that used for forming a P-well 118 and an N-well 119 for the logic device. Reference numerals 112a to 112d denote isolation layers, 120a denotes an LDD region, 121a, 122a, and 122b denote source/drain regions, 123a denotes a gate, and 124a denotes a silicide layer.
As described above, in the conventional method of manufacturing a semiconductor device, an additional mask for forming a drift region of high voltage (HV) DECMOS device is used, so the number of masks in the full process may be the same or increased.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention, and therefore, it may contain information that does not form prior art or other information that is already known in this or any other country to a person of ordinary skill in the art.